Conventionally, in designing hardware (circuit) for realization of a desired function, it is essential to conduct logic verification to see if there is no omission in the design, as a process in a preliminary stage before actual manufacture of the hardware. Specifically, a verification scenario is produced according to the hardware design, and logic verification is carried out using an output resulting from entry of the verification scenario.
In addition, verification coverage is determined to evaluate objectively the verification process under the verification scenario produced as stated above. The verification coverage refers to information as an index of absence of sufficient patterns of simulations with a verification target. Specifically, if all patterns of simulations requiring verification constitute a parent population, a coverage ratio is determined from a proportion of the number of patterns of executed simulations, and provided as verification coverage, for example. In this case, it is deemed that verification accuracy becomes higher with an increase in verification coverage (coverage ratio).
However, there is a problem with this method by which “all patterns of simulations requiring verification” are extracted as a parent population. Such all patterns of simulations as a parent population refer to a coverage standard. If some of patterns extracted as a coverage standard are virtually unuseful in verification, actual efficiency of verification may not be improved even with a high coverage ratio in the simulation.
Accordingly, methods called path coverage and code coverage are currently utilized to extract patterns comprehensively in line with a specific standard. Path coverage uses patterns to verify all paths generating a state transition in registers included in a verification target circuit. Therefore, in the path coverage method, an aggregation of these patterns constitute a coverage standard. Code coverage, also called line coverage, uses patterns to verify paths in relation to input/output of registers describing source codes, which are equivalent to a verification target circuit. In the code coverage method, an aggregation of these patterns constitute a coverage standard.
Related documents are as follows: Japanese Patent Application Unexamined Publication No. 2006-190209 (patent document 1); Japanese Patent Application Unexamined Publication No. 2006-201980 (patent document 2); and Harry. D. Foster, et al, “Assertion-Based Design” (2nd Edition), “Programming Code Metrics”, pp. 129 to 130 (non-patent document 1).
However, the conventional coverage standards as stated above are inefficient in many aspects and have difficulty in serving as standards of determination for improvement of verification efficiency. Specifically, in the path coverage method, extracted patterns cover all parameter values that may be input into registers included in a verification target circuit. Therefore, a nearly infinite number of patterns may be generated depending on the number and kinds of registers. As a result, there is a problem that a value of a denominator in calculation of verification coverage becomes large, which thereby requires an enormous amount of processing time.
Further, in the code coverage method, when a verification target circuit has a plurality of conditional branches, some path requiring verification may be omitted. As a result, insufficient patterns are provided and thus verification coverage is decreased in reliability, resulting in a low accuracy of verification.